Project information

• Category: Electrical Engineering Project
• Organization: University of Virginia
• Project Date: Spring 2020
• Project File: CSAProject.pptx

For this project I worked with one other electrical engineer to create a 16-Bit Carry Skip Adder (CSA) in Cadence Virtuoso. As part of the project requirements, we developed a high level digital logic design of the Carry Skip Adder. Thereafter from this design we created P-MOS and N-MOS layouts as well as verified the functionality of the final product using custom testbenches. After proving basic functionality we also calculated the performance metrics of the integrated circuit including power consumption, critical path delay, and power delay product. Click on the link above for the PowerPoint presentation for this project.